| [외국계 반도체 제조사] Principle Engineer- VLSI Design Engineering | |
|---|---|
| 구분 | 국외 |
| 직종 | 연구개발(R&D)/설계 |
| 회사소개 | |
| 업무내용/자격요건 | [포지션 명] Principal Engineer, VLSI Design Engineering [주요 업무] - RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure - Balance design trade-offs with modularity, scalability, power, area, and performance. - Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements - Participating in Post-Si evaluation and debug - Drive cross function support for productization - Technical guidance and mentoring of junior engineers ? [자격?요건] - MSEE plus 10 years of relevant experience - Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design - Working knowledge of the entire Logic design flow from RTL to GDSII?(RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification) - Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase - Excellent communication (written and verbal) and interpersonal skills [우대 요건] - Experience developing digital circuit designs for low power operating conditions - Working knowledge of device physics and process - Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits - Proficiency with following Digital design tools - Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing - Synopsys Primetime or Cadence Tempus - Place and Route - Synopsys ICC or Cadence Encounter or Innovus - Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints) - Programming experience in C, C++, Python or Perl [지원방법 및 담당자] -지원 방법 : 영문 및 국문 이력서 이메일 지원*영문 이력서 필수 -헤드헌팅사 피너클써치 문소영 이사 010-4580-1115 / jenni@pinn.co.kr |
| 기타사항 | 학력:대졸이상, 나이:0년-0년 출생자, 성별:무관, 외국어:무관 직급/직책:과장 ~ 부장 근무지:서울시 강남구 |
| 담당자 | 담당컨설턴트: 문소영 상무 연락처: 010-4580-1115 / 010-4580-1115 이메일: jenni@pinn.co.kr |